Conventional technologies for reducing power semiconductor device gate to drain capacitance while increasing voltage resistance and current are still plagued with technical limitations. Because of growing demands for high frequency switch power devices, an urgent need exists to resolve these technical difficulties and limitations. For power transistors including MOSFET and IGBT (insulated-gate bipolar transistor), a new device configuration and manufacturing process are necessary to reduce the speed-limiting capacitance between the gate and the drain of these switching power devices.
Gate to drain capacitance, Cgd degrades switching performance of MOSFETs. Various techniques have been proposed for reducing Cgd. One proposal, described in U.S. Pat. No. 7,557,409, uses a super trench MOSFET, wherein a source electrode is buried in the lower portion of the trench to reduce the gate-to-drain capacitance, improving the ability of the MOSFET to operate at high frequencies. The trench buried source electrode is insulated from the epitaxial layer and semiconductor substrate but is in electrical contact with the source region. The substrate advantageously includes a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs.
Another proposal has been to increase the thickness of the gate oxide layer at the bottom of the trench, as suggested in U.S. Pat. No. 4,914,058 to Blanchard. In Blanchard, the MOSFET as an N-channel device is formed in an epitaxial (epi) layer that is grown on an N+ substrate. A trench extends through the epi layer and into N+ substrate. The epi layer is generally doped with an N-type impurity such as phosphorus. The epi layer also includes an N+ source region and a P body, both of which are contacted by a metal layer. The background N-type doping of the epi layer is found in an N-drift region. The N+ substrate and the N-drift region represent the drain of the Blanchard MOSFET.
The sidewalls of the trench are lined with a gate oxide layer, and trench is filled with a gate electrode, which is typically made of polycrystalline silicon. (polysilicon) that is doped heavily to make it conductive. A thin gate oxide was grown on the walls and floor of trench. Noteworthy is that the Blanchard MOSFET has sidewalls that are lined but not independent structures such as gates. At the bottom of the trench is a thick oxide layer that serves to reduce the capacitance between the polysilicon gate and the drain (the N+ substrate and the N-drift region).
Baliga discloses in U.S. Pat. No. 5,998,833, and in particular FIG. 3, a DMOS (double-diffused metal-oxide-semiconductor) cell as an example of conventional art. Baliga's disclosure shows use of a source electrode 128a underneath the trenched gate 127 to reduce the gate-to-drain capacitance. Both source electrode 128a and trenched gate 127 are in the trench defined by side walls 120a. The gate of the DMOS cell is divided into two segments. The gate-to-drain capacitance is reduced because contributions to capacitance from the gate-drain overlapping areas are eliminated.
Another example of conventional art is shown as FIG. 1 in U.S. Pat. No. 6,690,062. This reference teaches an improvement in the switching behavior of a trenched MOS power transistor by providing a shielding electrode 17 in an edge region 4. The shielding electrode surrounds at least sections of an active cell array 2. Gate electrodes 10 are configured in trenches 9. There is a capacitance between an edge metallization gate structure 20 and a drain zone 16. The shielding electrode 17 located in the edge region 4 reduces the capacitance between an edge gate structure and a drain zone 16 and hence reduces the gate-drain capacitance of the transistor.
The above described transistor configurations still have a common difficulty. The source electrode disposed on the trench bottom is connected to the source voltage through an edge area of the semiconductor power device. This inevitably increases the source electrode resistance. Furthermore, the extra masks needed to create such connection also increase the cost of manufacturing. More importantly, decreasing the capacitance between gate and source to achieve higher switching speed leads to poor voltage resistance at high current because the rate of change in current becomes steep during the switching process.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide a new manufacturing method and device configuration in forming the power devices such that the above discussed problems and limitations can be resolved.
An electronic device includes a drift region having a first conductivity type and a gate including a plurality of doped regions formed in the drift region and having a second conductivity type. The doped regions have a dopant concentration greater than 2.2.times.10.sup.19 cm.sup.−3
A vertical SiC-MOSFET formed in this way is expected to be utilized as a switching device having low ON-resistance and switchable at high speed in power conversion equipment such as an inverter for motor control and an uninterruptible power supply (UPS). However, when high voltage is applied between a source and a drain, the high voltage is applied not only to an active region through which current flows during on-time but also to an edge termination structure region that is disposed in a peripheral portion of the active region and that sustains the breakdown voltage. When high voltage is applied, the edge termination structure region has a depletion layer spreading in a lateral direction (a direction parallel to a substrate principal plane) and is, therefore, susceptible to electrical charge of the substrate surface. As a result, breakdown characteristics become unstable.
Another complicated proposed solution presented by Nobuyuki et al. in JP2013-069852A “Semiconductor Device” is to build the source electrode deep in the trench, but add extra insulation lining the trench near the trench top, between the source and the base. See FIG. 1. This figure shows parallel-arranged trenches 10 with centrally positioned source electrodes 20 with gates 30 arranged near the channel tops between source 20 and base P regions (labelled “P”). A higher breakdown voltage is achieved by making the hatched insulation layer thicker in region 50.
In particular, this teaches increased insulation thickness between gate and source than between gate and the inside wall semiconductor. However, such structure is sensitive to overvoltage at high frequency switching. This disclosure continues the general teaching in this field to add structures, such as thicker insulation regions, to the trenches and in their peripheries. In particular, However, such added complexity is undesirable and generally increases space usage, and conflicts with the need for increased current capacity. In particular, peripheral trenches taught as a solution undesirably add cost and require space.